FIG. 1 shows a typical prior art p-channel MOS transistor formed using a self-aligned process. In the exemplary device of FIG. 1, an n.sup.+ substrate 10 has an n.sup.- epitaxial layer 11 formed thereon. Highly doped p.sup.+ sources 12 and drain 13 are formed on either side of gates 14 in the surface of epitaxial layer 11. Aluminum source contacts 16 and drain contact 17 provide electrical contact to sources 12 and drain 13, respectively.
The shallow p.sup.+ diffused regions forming sources 12 and drain 13 are formed simultaneously using the same process steps. Generally, to form sources 12 and drain 13, gates 14 are first formed, and the surface of epitaxial layer 11 is exposed on both sides of gates 14. P-type dopants are then implanted using gates 14 as a mask so that the sources 12 and drain 13 become self-aligned with gates 14. A subsequent diffusion step causes the sources 12 and drain 13 to slightly diffuse under gates 14. Using a self-aligned method obviates the need for critical masking and alignment steps for aligning a gate with source and drain regions.
As illustrated in FIG. 1, gates 14 overlap p.sup.+ sources 12 by an underdiffusion length U.sub.s. This overlap, separated by an oxide layer 15, creates a certain parasitic capacitance C.sub.gs between sources 12 and their associated gates 14. The magnitude of capacitance C.sub.gs depends upon the underdiffusion length U.sub.s, where the longer the underdiffusion length U.sub.s, the larger the capacitance C.sub.gs. Similarly, gates 14 overlap the p.sup.+ drain 13 by an underdiffusion length U.sub.d, resulting in a certain parasitic capacitance C.sub.gd between drain 13 and each of gates 14.
Since sources 12 and drain 13 are formed simultaneously during the same self-aligned process, the underdiffusion lengths U.sub.s and U.sub.d are equal.
Parasitic gate-drain capacitance C.sub.gd and parasitic gate-source capacitance C.sub.gs adversely affect the frequency response of MOS transistors. Moreover, excessive underdiffusion is a waste of valuable die area. Therefore, underdiffusion lengths U.sub.s and U.sub.d are normally minimized to maximize circuit speed and packing density.
Many circuits formed using MOS transistors call for a certain value capacitor to be inserted between a gate and a drain of a transistor. Typically, this capacitor is formed by a conductive plate of a selected area overlying and insulated from a diffused region or by connecting the sources and drains of a number of MOS transistors in parallel to make use of the parasitic capacitances of those MOS transistors. Therefore, when the need for a relatively high-value gate-drain capacitor arises, one or more capacitors must be formed on the semiconductor wafer surface. These extra capacitor(s) require additional die area. Further, if an upper plate of a capacitor is to be formed overlying a diffused bottom plate, this greatly complicates forming MOS transistors using a self-aligned gate/source/drain process where the gate is formed before the implantation of dopants.
For the foregoing reasons, there is a need for a method to form both a self-aligned MOS transistor and a gate-drain capacitor of a selected value without requiring significant additional die area and critical mask alignment steps to form the capacitor.